Diseño e implementación mediante síntesis de alto nivel de un IP para el filtrado y clasificación de paquetes TCP/IP

Abstract

This paper presents the work done to design a packet classifier implemented on a FPGA. The target of this IP block is to accelerate the decision process of a network security system. This block decides whether a packet is sent either to a DPI block or Ethernet interface. The decision is made by checking the values of different fields within the headers of the Ethernet and IP layers.