A quantitative understanding of the performance of reconfigurable coprocessors

Abstract

The goal of this work is to explore the architectural behavior of FPGA-based coprocessors that are part of general-purpose computer systems. Our analysis shows maximum performance improvements of up to two orders of magnitude in comparison with current high-performance processors. However, the performance benefits exhibited by reconfigurable coprocessors may be deeply influenced by some design parameters. We have studied the impact of hardware capacity, reconfiguration time, memory organization, and system bus bandwidth on the performance achieved by FPGA-based coprocessors. Our results suggest that an unappropriated bandwidth both for the reconfigurable data-path and host bus can degrade enormously the performance improvement. Since the variation of bus bandwidths encountered in contemporary computer systems is substantial, we found that reconfigurable coprocessors are more efficient when placed as close to the processor as possible without being part of its data-path.