Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/49670
| Título: | Fast adder design in dynamic logic | Autores/as: | Montiel-Nelson, Juan A. Nooshabadi, Saeid Navarro-Botello, Victor |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Logic design CMOS logic circuits adders Pulse inverters Delay effects, et al. |
Fecha de publicación: | 2007 | Publicación seriada: | Midwest Symposium on Circuits and Systems | Conferencia: | 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference | Resumen: | This paper presents the design of fast adder structures using a new CMOS logic family - Feedthrough Logic (FTL). The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (30.1%), and similar combined delay, power consumption and active area product (0.9% worst). | URI: | http://hdl.handle.net/10553/49670 | ISBN: | 1424411769 | ISSN: | 1548-3746 | DOI: | 10.1109/MWSCAS.2007.4488706 | Fuente: | Midwest Symposium on Circuits and Systems[ISSN 1548-3746] (4488706), p. 851-854 |
| Colección: | Actas de congresos |
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