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Title: Fast adder design in dynamic logic
Authors: Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
Navarro-Botello, Victor 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Logic design
CMOS logic circuits
Pulse inverters
Delay effects, et al
Issue Date: 2007
Journal: Midwest Symposium on Circuits and Systems 
Conference: 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference 
Abstract: This paper presents the design of fast adder structures using a new CMOS logic family - Feedthrough Logic (FTL). The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (30.1%), and similar combined delay, power consumption and active area product (0.9% worst).
ISBN: 1424411769
ISSN: 1548-3746
DOI: 10.1109/MWSCAS.2007.4488706
Source: Midwest Symposium on Circuits and Systems[ISSN 1548-3746] (4488706), p. 851-854
Appears in Collections:Actas de congresos
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