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http://hdl.handle.net/10553/49651
| Título: | Power delay tradeoff using the genetic algorithm | Autores/as: | Sosa González, Carlos Javier Montiel-Nelson, Juan A. Nooshabadi, Saeid |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Delay Genetic algorithms Energy consumption Optimization methods CMOS technology, et al. |
Fecha de publicación: | 2009 | Publicación seriada: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 | Conferencia: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 | Resumen: | This paper presents a novel methodology to obtain the entire power versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using genetic algorithm (GA). In order to evaluate the proposed GA method a wide set of two-level and multi-level networks from the MCNC'91 benchmark suite was processed. The proposed optimization using the GA methodology is several times better than linear programming (LP) technique in terms of CPU time. On the other hand the minimum power dissipation obtained by GA and LP methods are very close to each other to within 0.3%. | URI: | http://hdl.handle.net/10553/49651 | ISBN: | 9781424445219 | DOI: | 10.1109/ISCIT.2009.5341062 | Fuente: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 (5341062), p. 1344-1347 |
| Colección: | Actas de congresos |
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