High performance single supply CMOS 0.45–1 V input to 1.1 V output level up shifter

Abstract

This paper presents the design of a single supply CMOS level up shifter for low voltage and low energy consumption. The proposed voltage level converter is implemented using low threshold voltage transistors in 65 nm CMOS technology. The shifter circuit designed for an output of 1.1 V was verified, through the post layout simulation, to be functional for an input voltage range of 0.45-1 V. We compare our work with several other level shifters. With a 50 fF of capacitive load, the shifter's energy-delay product is a 40% lower than a similar single supply level up shifter. Moreover, the measurements on the fabricated dies show that the proposed structure is able to drive a double capacitive load of up to 105 fF, without any impact on the static power consumption. Monte-Carlo analysis demonstrates the robustness of the proposed shifter within a 3 sigma device mismatch.