EDAC implementation on a data lossless compressor compliant with the CCSDS 121.0-B-3 standard

Abstract

Electronics embarked on satellites are susceptible to radiation effects, which can cause a partial malfunction of the system, modifying its behaviour and possibly deriving in a reduction of the space mission lifetime. These effects are even more critical in reprogrammable devices, such as FPGAs, whose memory resources are not always protected to unexpected changes. In this work, a technology-independent EDAC mechanism is implemented on an IP core fully compliant with the CCSDS 121.0-B-3 lossless compression standard, which describes a low-complexity and high performance algorithm for on-board data compression. Critical memories are identified, since they are candidates to be protected, and area overhead is estimated in case they are implemented using only logic resources, getting rid in this case of the necessity of the EDAC mechanism. Finally, a comparison with the IP version without EDAC is presented, in order to reflect the impact of implementing this method and observing a penalty of around a 0.6% and a maximum of 23%, in terms of resources utilization and maximum clock frequency, respectively.