Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/77075
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Saiz-Perez, Jose Luis | en_US |
dc.contributor.author | Del Pino, Javier | en_US |
dc.contributor.author | Mayor Duarte, Daniel | en_US |
dc.contributor.author | Khemchandani, Sunil L. | en_US |
dc.contributor.author | San Miguel Montesdeoca, Mario | en_US |
dc.contributor.author | Mateos Angulo, Sergio | en_US |
dc.date.accessioned | 2021-01-12T08:23:15Z | - |
dc.date.available | 2021-01-12T08:23:15Z | - |
dc.date.issued | 2020 | en_US |
dc.identifier.isbn | 9781728191324 | en_US |
dc.identifier.other | Scopus | - |
dc.identifier.uri | http://hdl.handle.net/10553/77075 | - |
dc.description.abstract | A Distributed Power Amplifier (DPA) with a tapered drain line is presented in this paper. The drain line impedance tapering technique allows to obtain a higher output power and efficiency compared to the conventional approach, whereas a constant drain line impedance avoids impedance changes in the power supply drive signal. The design was implemented using the D01GH/Si technology provided by the foundry OMMIC. The DPA achieves a Psat of 32 dBm and a flat gain over 14 dB in a frequency range that ranges from 1 to 8 GHz. Moreover, this circuit achieves a Power Added Efficiency (PAE) of 50%. Finally, the occupied area of the DPA is 2.2x1.2mm2 excluding pads. | en_US |
dc.language | eng | en_US |
dc.source | 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) | en_US |
dc.subject | 3325 Tecnología de las telecomunicaciones | en_US |
dc.subject.other | Distributed Pa | en_US |
dc.subject.other | Gan | en_US |
dc.subject.other | Ommic | en_US |
dc.subject.other | Power Added Efficiency (Pae) | en_US |
dc.title | Distributed power amplifier in GaN technology with tapered drain lines | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 35th Conference on Design of Circuits and Integrated Systems - DCIS 2020 | en_US |
dc.identifier.doi | 10.1109/DCIS51330.2020.9268621 | en_US |
dc.identifier.scopus | 85098618948 | - |
dc.contributor.authorscopusid | 57221272012 | - |
dc.contributor.authorscopusid | 56740582700 | - |
dc.contributor.authorscopusid | 57188844909 | - |
dc.contributor.authorscopusid | 9639770800 | - |
dc.contributor.authorscopusid | 57200522353 | - |
dc.contributor.authorscopusid | 57188853360 | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.utils.revision | Sí | en_US |
dc.date.coverdate | Noviembre 2020 | en_US |
dc.identifier.conferenceid | events128235 | - |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
item.fulltext | Sin texto completo | - |
item.grantfulltext | none | - |
crisitem.author.dept | GIR IUMA: Tecnología Microelectrónica | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Tecnología Microelectrónica | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0003-2610-883X | - |
crisitem.author.orcid | 0000-0002-3747-570X | - |
crisitem.author.orcid | 0000-0003-0087-2370 | - |
crisitem.author.orcid | 0000-0001-7296-021X | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Del Pino Suárez, Francisco Javier | - |
crisitem.author.fullName | Mayor Duarte, Daniel | - |
crisitem.author.fullName | Khemchandani Lalchand, Sunil | - |
crisitem.author.fullName | San Miguel Montesdeoca, Mario | - |
crisitem.author.fullName | Mateos Angulo, Sergio | - |
Appears in Collections: | Actas de congresos |
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