Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/75353
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dc.contributor.authorBarrios Alfaro, Yubalen_US
dc.contributor.authorRodríguez, Alfonsoen_US
dc.contributor.authorSánchez Clemente, Antonio Joséen_US
dc.contributor.authorPérez, Arturoen_US
dc.contributor.authorLópez, Sebastiánen_US
dc.contributor.authorOtero, Andrésen_US
dc.contributor.authorde la Torre, Eduardoen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.date.accessioned2020-11-11T07:58:12Z-
dc.date.available2020-11-11T07:58:12Z-
dc.date.issued2020en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/75353-
dc.description.abstractThis paper describes a novel hardware implementation of a lossy multispectral and hyperspectral image compressor for on-board operation in space missions. The compression algorithm is a lossy extension of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless standard that includes a bit-rate control stage, which in turn manages the losses the compressor may introduce to achieve higher compression ratios without compromising the recovered image quality. The algorithm has been implemented using High-Level Synthesis (HLS) techniques to increase design productivity by raising the abstraction level. The proposed lossy compression solution is deployed onto ARTICo3, a dynamically reconfigurable multi-accelerator architecture, obtaining a run-time adaptive solution that enables user-selectable performance (i.e., load more hardware accelerators to transparently increase throughput), power consumption, and fault tolerance (i.e., group hardware accelerators to transparently enable hardware redundancy). The whole compression solution is tested on a Xilinx Zynq UltraScale+ Field-Programmable Gate Array (FPGA)-based MPSoC using different input images, from multispectral to ultraspectral. For images acquired by the Airborne Visible/Infrared Imaging Spectrometer (AVIRIS), the proposed implementation renders an execution time of approximately 36 s when 8 accelerators are compressing concurrently at 100 MHz, which in turn uses around 20% of the LUTs and 17% of the dedicated memory blocks available in the target device. In this scenario, a speedup of 15.6× is obtained in comparison with a pure software version of the algorithm running in an ARM Cortex-A53 processor.en_US
dc.languageengen_US
dc.relation.ispartofElectronics (Switzerland)en_US
dc.sourceElectronics (Switzerland)[EISSN 2079-9292],v. 9 (10), p. 1-23, (Octubre 2020)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherCcsdsen_US
dc.subject.otherFault-Toleranceen_US
dc.subject.otherHardware Accelerationen_US
dc.subject.otherHyperspectral Imagingen_US
dc.subject.otherLossy Data Compressionen_US
dc.subject.otherOn-Board Processingen_US
dc.titleLossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform†en_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.3390/electronics9101576en_US
dc.identifier.scopus85091624397-
dc.contributor.authorscopusid57201297173-
dc.contributor.authorscopusid56972626600-
dc.contributor.authorscopusid57211429595-
dc.contributor.authorscopusid56236355600-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid35868116400-
dc.contributor.authorscopusid6603668216-
dc.contributor.authorscopusid35609452100-
dc.identifier.eissn2079-9292-
dc.description.lastpage23en_US
dc.identifier.issue10-
dc.description.firstpage1en_US
dc.relation.volume9en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.utils.revisionen_US
dc.date.coverdateOctubre 2020en_US
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-INGen_US
dc.description.sjr0,36
dc.description.jcr2,397
dc.description.sjrqQ2
dc.description.jcrqQ3
dc.description.scieSCIE
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0001-6186-9971-
crisitem.author.orcid0000-0002-2142-7885-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameBarrios Alfaro,Yubal-
crisitem.author.fullNameSánchez Clemente,Antonio José-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
Colección:Artículos
miniatura
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