Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/74673
Título: Architectural support for real-time task scheduling in SMT processors
Autores/as: Cazorla, Francisco J.
Fernández, Enrique 
Knijnenburg, Peter M.W.
Ramirez, Alex
Sakellariou, Rizos
Valero, Mateo
Clasificación UNESCO: 3304 Tecnología de los ordenadores
330417 Sistemas en tiempo real
330406 Arquitectura de ordenadores
Palabras clave: ILP
Multi-threading
Performance predictability
Real time
Scheduling, et al.
Fecha de publicación: 2005
Conferencia: CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 
Resumen: In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, they also interfere with each other. As a result, execution times of applications become highly unpredictable and dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a real-time system. In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Nor do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real-time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.
URI: http://hdl.handle.net/10553/74673
ISBN: 978-1-59593-149-8
DOI: 10.1145/1086297.1086320
Fuente: CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, p. 166-176, (Diciembre 2005)
Colección:Actas de congresos
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