Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/74673
Campo DC Valoridioma
dc.contributor.authorCazorla, Francisco J.en_US
dc.contributor.authorFernández, Enriqueen_US
dc.contributor.authorKnijnenburg, Peter M.W.en_US
dc.contributor.authorRamirez, Alexen_US
dc.contributor.authorSakellariou, Rizosen_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2020-10-07T19:46:30Z-
dc.date.available2020-10-07T19:46:30Z-
dc.date.issued2005en_US
dc.identifier.isbn978-1-59593-149-8en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/74673-
dc.description.abstractIn Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. However, since threads share many resources, they also interfere with each other. As a result, execution times of applications become highly unpredictable and dependent on the context in which an application is executed. Obviously, this poses problems if an SMT is to be used in a real-time system. In this paper, we propose two novel hardware mechanisms that can be used to reduce this performance variability. In contrast to previous approaches, our proposed mechanisms do not need any information beyond the information already known by traditional job schedulers. Nor do they require extensive profiling of workloads to determine optimal schedules. Our mechanisms are based on dynamic resource partitioning. The OS level job scheduler needs to be slightly adapted in order to provide the hardware resource allocator some information on how this resource partitioning needs to be done. We show that our mechanisms provide high stability for SMT architectures to be used in real-time systems: the real time benchmarks we used meet their deadlines in more than 98% of the cases considered while the other thread in the workload still achieves high throughput.en_US
dc.languageengen_US
dc.sourceCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, p. 166-176, (Diciembre 2005)en_US
dc.subject3304 Tecnología de los ordenadoresen_US
dc.subject330417 Sistemas en tiempo realen_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherILPen_US
dc.subject.otherMulti-threadingen_US
dc.subject.otherPerformance predictabilityen_US
dc.subject.otherReal timeen_US
dc.subject.otherSchedulingen_US
dc.subject.otherSMTen_US
dc.subject.otherThread-level parallelismen_US
dc.titleArchitectural support for real-time task scheduling in SMT processorsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systemsen_US
dc.identifier.doi10.1145/1086297.1086320en_US
dc.identifier.scopus29144505105-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid6603587864-
dc.contributor.authorscopusid7401734996-
dc.contributor.authorscopusid6701361478-
dc.contributor.authorscopusid24475914200-
dc.description.lastpage176en_US
dc.description.firstpage166en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.date.coverdateDiciembre 2005en_US
dc.identifier.conferenceidevents121297-
dc.identifier.ulpgces
dc.description.ggs3
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate24-09-2005-
crisitem.event.eventsenddate27-09-2005-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.fullNameFernández García, Enrique-
Colección:Actas de congresos
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