Adaptive L2 cache for chip multiprocessors

Abstract

An open question in chip multiprocessors is how to organize large on-chip cache resources. Its answer must consider hit/miss latencies, energy consumption, and power dissipation. To handle this diversity of metrics, we propose the Amorphous Cache, an adaptive heterogeneous architecture for large cache memories that provides new ways of configurability. The Amorphous Cache adapts to fit the code and data by using partial array shutdowns during run-time. Its cache configuration can be resized and the set associativity changed. Four reconfiguration modes can be used, which prioritize either IPC, processor power dissipation, energy consumption of processor and DIMM memory module, or processor power(2) x delay product. They have been evaluated in CMPs that use private L2 caches and execute independent tasks. When one of the cores of a CMP with 4-MB L2 shared-cache is used as baseline, the maximum average improvements in IPC, power dissipation, energy consumption, and power(2) x delay achieved by a single core with 2-MB private L2 Amorphous Cache are 14.2%, 44.3%, 18.1%, and 29.4% respectively.