|Title:||A cost effective architecture for vectorizable numerical and multimedia applications||Authors:||Quintana, Francisca
|UNESCO Clasification:||330406 Arquitectura de ordenadores||Issue Date:||2001||Conference:||13th Annual Symposium on Parallel Algorithms and Architectures (SPAA 2001)||Abstract:||This paper analyzes the performance of vector-dominated regions of code in numerical and multimedia applications in a superscalar+vector architecture and compares it to an 8-way superscalar processor. The ability to split a program's execution into scalar and vector regions allows us to show that (1) as expected, the vector unit is much better than the wide issue superscalar at executing the vector-dominated regions of the code; (2) on the scalar regions, the 8-way superscalar, although better than a 4-way superscalar, is clearly not worth the extra complexity in terms of extra transistors and potential cycle time limitations. Overall, the vector-enhanced superscalar is from 6% to 303% better than an 8-way superscalar. We also present detailed data on the performance of the memory system, which is usually the key limiting factor when running numerical and multimedia applications. We evaluate two additional cache designs that try to alleviate problems created by non-unit stride memory references.||URI:||http://hdl.handle.net/10553/72945||ISBN:||978-1-58113-409-4||DOI:||10.1145/378580.378602||Source:||Annual ACM Symposium on Parallel Algorithms and Architectures, p. 103-112, (Enero 2001)|
|Appears in Collections:||Actas de congresos|
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