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Title: A case for merging the ILP and DLP paradigms
Authors: Quintana, F. 
Espasa, R
Valero, M
UNESCO Clasification: 330406 Arquitectura de ordenadores
Issue Date: 1998
Conference: 6th Euromicro Workshop on Parallel and Distributed Processing (PDP 98) 
Abstract: The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We will show that this architecture can reach a performance equivalent to a superscalar processor that sustained 10 instructions per cycle. We will see that the machine exploiting both types of parallelism improves upon the ILP-only machine by factors of 1.5-1.8. We also present a study on the scalability of both paradigms and show that, when we increase resources to reach a 16-issue machine, the advantage of the ILP+DLP machine over the ILP-only machine increases up to 2.0-3.45. While the peak achieved IPC for the ILP machine is 4, the ILP+DLP machine exceeds 10 instructions per cycle.
ISBN: 978-0-8186-8332-9
DOI: 10.1109/EMPDP.1998.647201
Source: Proceedings Of The Sixth Euromicro Workshop On Parallel And Distributed Processing - Pdp '98, p. 217-224, (1998)
Appears in Collections:Actas de congresos
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