Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/72706
Title: Dynamically controlled resource allocation in SMT processors
Authors: Cazorla, Francisco J.
Ramirez, Alex
Valero, Mateo
Fernández, Enrique 
UNESCO Clasification: 330412 Dispositivos de control
3304 Tecnología de los ordenadores
Issue Date: 2004
Conference: 37th International Symposium on Microarchitecture - MICRO-37 2004 
Abstract: SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for these resources. The way critical resources are distributed among threads determines the final performance. Currently, processor resources are distributed among threads as determined by the fetch policy that decides which threads enter the processor to compete for resources. However, current fetch policies only use indirect indicators of resource usage in their decision, which can lead to resource monopolization by a single thread or to resource waste when no thread can use them. Both situations can harm performance and happen, for example, after an L2 cache miss. In this paper, we introduce the concept of dynamic resource control in SMT processors. Using this concept, we propose a novel resource allocation policy for SMT processors. This policy directly monitors the usage of resources by each thread and guarantees that all threads get their fair share of the critical shared resources, avoiding monopolization. We also define a mechanism to allow a thread to borrow resources from another thread if that thread does not require them, thereby reducing resource under-use. Simulation results show that our dynamic resource allocation policy outperforms a static resource allocation policy by 8%, on average. It also improves the best dynamic resource-conscious fetch policies like FLUSH++ by 4%, on average, using the harmonic mean as a metric. This indicates that our policy does not obtain the ILP boost by unfairly running high ILP threads over slow memory-bounded threads. Instead, it achieves a better throughput-fairness balance.
URI: http://hdl.handle.net/10553/72706
ISBN: 0-7695-2126-6
ISSN: 1072-4451
DOI: 10.1109/MICRO.2004.17
Source: Proceedings of the Annual International Symposium on Microarchitecture, MICRO, p. 171-182, (Diciembre 2004)
Appears in Collections:Actas de congresos
Show full item record

SCOPUSTM   
Citations

116
checked on Jul 12, 2020

Page view(s)

11
checked on Jul 11, 2020

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.