Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/72656
Campo DC Valoridioma
dc.contributor.authorMoure, Juan C.en_US
dc.contributor.authorBenítez, Domingoen_US
dc.contributor.authorRexachs, Dolores I.en_US
dc.contributor.authorLuque, Emilioen_US
dc.date.accessioned2020-05-20T09:27:35Z-
dc.date.available2020-05-20T09:27:35Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-59593-282-2en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/72656-
dc.description.abstractHigh prediction bandwidth enables performance improvements and power reduction techniques. This paper explores a mechanism to increase prediction width (instructions per prediction) by predicting instruction traces. Our analysis shows that predicting traces including multiple branches is not significantly less accurate than predicting single branches. A novel Local Trace Predictor organization is proposed. It increases prediction width without reducing the ratio of prediction accuracy versus memory resources with respect to a Basic Block Predictor.Compared to the previously proposed Next-Trace Predictor, the Local Trace Predictor reduces memory requirements by codifying trace predictions, and by limiting the number of traces starting at the same instruction to 2 or 4. The limit lessens prediction width only slightly, and does not affect prediction accuracy. The overall result is that the Local Trace Predictor outperforms the Next-Trace Predictor for sizes higher than 12 KBytes.en_US
dc.languageengen_US
dc.sourceProceedings of the International Conference on Supercomputing, p. 55-65, (Diciembre 2006)en_US
dc.subject1203 Ciencia de los ordenadoresen_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.subject.otherBranch Predictionen_US
dc.subject.otherHigh Bandwidth Fetch Mechanismen_US
dc.titleWide and efficient trace prediction using the local trace predictoren_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference20th Annual International Conference on Supercomputing, ICS 2006en_US
dc.identifier.doi10.1145/1183401.1183411en_US
dc.identifier.scopus34547409308-
dc.contributor.authorscopusid57188672353-
dc.contributor.authorscopusid7003286582-
dc.contributor.authorscopusid6506076654-
dc.contributor.authorscopusid7005407181-
dc.description.lastpage65en_US
dc.description.firstpage55en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionNoen_US
dc.date.coverdateDiciembre 2006en_US
dc.identifier.conferenceidevents121323-
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR SIANI: Modelización y Simulación Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0003-2952-2972-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameBenítez Díaz, Domingo Juan-
crisitem.event.eventsstartdate28-06-2006-
crisitem.event.eventsenddate01-07-2006-
Colección:Actas de congresos
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