Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/70307
Title: Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
Authors: Leon, Raquel
Dominguez, Adrian
Carballo, Pedro P. 
Nunez, Antonio 
Keywords: Deep Packet Inspection
Esl
Mentor Vista
System On Chip
Tlm
Virtual Platform
Issue Date: 2019
Journal: 2019 34Th Conference On Design Of Circuits And Integrated Systems, Dcis 2019
Abstract: © 2019 IEEE. Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures.
URI: http://hdl.handle.net/10553/70307
ISBN: 9781728154589
DOI: 10.1109/DCIS201949030.2019.8959882
Source: 2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019
Appears in Collections:Actas de congresos
Fuentes externas
Show full item record

Page view(s)

11
checked on Mar 28, 2020

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.