Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/70307
Title: Deep packet inspection through virtual platforms using system-on-chip FPGAs
Authors: León Martín, Sonia Raquel 
Domínguez Hernández, Adrián 
Carballo, Pedro P. 
Nunez, Antonio 
UNESCO Clasification: 3306 Ingeniería y tecnología eléctricas
Keywords: Deep Packet Inspection
Esl
Mentor Vista
System On Chip
Tlm, et al
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers (IEEE) 
Conference: 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019 
Abstract: Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures.
URI: http://hdl.handle.net/10553/70307
ISBN: 978-1-7281-5458-9
DOI: 10.1109/DCIS201949030.2019.8959882
Source: 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, Spain, 2019
Appears in Collections:Actas de congresos
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