Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/70085
Título: Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiation
Autores/as: Sánchez Clemente, Antonio José 
Barrios Alfaro, Yubal 
Santos, Lucana 
Sarmiento, Roberto 
Clasificación UNESCO: 3307 Tecnología electrónica
3325 Tecnología de las telecomunicaciones
Palabras clave: TMR effectiveness
SHyLoC compression IP core
Triple modular redundancy
Fecha de publicación: 2019
Publicación seriada: 2019 IEEE International Symposium On Defect And Fault Tolerance In Vlsi And Nanotechnology Systems, Dft 2019
Conferencia: 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 
Resumen: This work analyses the results of applying Triple Modular Redundancy (TMR) to the SHyLoC CCSDS-121 IP, a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless compression standard, a universal compressor specifically thought for space applications. The results obtained in a radiation experiment performed at the North Area new facilities at CERN are presented. The objective is to evaluate the robustness applying TMR to the design, by comparing to the unhardened implementation of the SHyLoC CCSDS-121 IP, when it is working under Ultra High Energy radiation. Both TMR and unhardened implementations of the SHyLoC CCSDS-121 IP were implemented in a Xilinx Zynq XC7Z020 System-on-Chip and radiated with Pb ions. Compression results were compared against a golden reference, obtaining a Mean Time To Failure (MTTF) a 40% higher for the TMR design than for the unhardened one.
URI: http://hdl.handle.net/10553/70085
ISBN: 9781728122601
DOI: 10.1109/DFT.2019.8875281
Fuente: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
Colección:Actas de congresos
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