Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/70085
Campo DC Valoridioma
dc.contributor.authorSánchez Clemente, Antonio Joséen_US
dc.contributor.authorBarrios Alfaro, Yubalen_US
dc.contributor.authorSantos, Lucanaen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.date.accessioned2020-02-05T12:52:19Z-
dc.date.available2020-02-05T12:52:19Z-
dc.date.issued2019en_US
dc.identifier.isbn9781728122601en_US
dc.identifier.otherScopus-
dc.identifier.urihttp://hdl.handle.net/10553/70085-
dc.description.abstractThis work analyses the results of applying Triple Modular Redundancy (TMR) to the SHyLoC CCSDS-121 IP, a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless compression standard, a universal compressor specifically thought for space applications. The results obtained in a radiation experiment performed at the North Area new facilities at CERN are presented. The objective is to evaluate the robustness applying TMR to the design, by comparing to the unhardened implementation of the SHyLoC CCSDS-121 IP, when it is working under Ultra High Energy radiation. Both TMR and unhardened implementations of the SHyLoC CCSDS-121 IP were implemented in a Xilinx Zynq XC7Z020 System-on-Chip and radiated with Pb ions. Compression results were compared against a golden reference, obtaining a Mean Time To Failure (MTTF) a 40% higher for the TMR design than for the unhardened one.en_US
dc.languageengen_US
dc.relation.ispartof2019 IEEE International Symposium On Defect And Fault Tolerance In Vlsi And Nanotechnology Systems, Dft 2019en_US
dc.source2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject3325 Tecnología de las telecomunicacionesen_US
dc.subject.otherTMR effectivenessen_US
dc.subject.otherSHyLoC compression IP coreen_US
dc.subject.otherTriple modular redundancyen_US
dc.titleEvaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiationen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019en_US
dc.identifier.doi10.1109/DFT.2019.8875281en_US
dc.identifier.scopus85074395560-
dc.contributor.authorscopusid57211429595-
dc.contributor.authorscopusid57201297173-
dc.contributor.authorscopusid54391653200-
dc.contributor.authorscopusid35609452100-
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.identifier.conferenceidevents121669-
dc.identifier.ulpgces
dc.contributor.buulpgcBU-INGen_US
dc.description.ggs3
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.event.eventsstartdate02-10-2019-
crisitem.event.eventsenddate04-10-2019-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2142-7885-
crisitem.author.orcid0000-0001-6186-9971-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSánchez Clemente, Antonio José-
crisitem.author.fullNameBarrios Alfaro,Yubal-
crisitem.author.fullNameSantos Falcón, Lucana-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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