Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/70067
|Title:||Hardware Implementation of the CCSDS 123.0-B-1 Lossless Multispectral and Hyperspectral Image Compression Standard by means of High Level Synthesis Tools||Authors:||Barrios, Yubal
Lopez, Jose Fco
|Issue Date:||2018||Journal:||Workshop On Hyperspectral Image And Signal Processing, Evolution In Remote Sensing||Abstract:||© 2018 IEEE. In this paper, a Field Programmable Gate Array (FPGA) implementation of the CCSDS 123.0-B-1 Lossless Multispectral and Hyperspectral Image Compression Algorithm is presented. This recommended standard provides a tradeoff between compression performance and computational complexity, which makes it suitable for onboard applications. A High-Level Synthesis (HLS) methodology is followed to reduce the implementation time of this complex algorithm in hardware, providing a comparison between two of the main solutions available in the market: Mentor Catapult C and Xilinx Vivado HLS. The final implementation is tested over a Xilinx Zynq-7000 FPGA-based MPSoC. The obtained results show the good features of the HLS solutions compared with a RTL alternative of the standard, in terms of maximum clock frequency and resources utilization, hightlighting the quality of the current HLS tools to obtain the equivalent RTL description.||URI:||http://hdl.handle.net/10553/70067||ISBN:||9781728115818||ISSN:||2158-6276||DOI:||10.1109/WHISPERS.2018.8747258||Source:||Workshop on Hyperspectral Image and Signal Processing, Evolution in Remote Sensing[ISSN 2158-6276],v. 2018-September|
|Appears in Collections:||Actas de congresos|
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.