Hardware Implementation of the CCSDS 123.0-B-1 lossless multispectral and hyperspectral image compression standard by means of high level synthesis tools

Abstract

In this paper, a Field Programmable Gate Array (FPGA) implementation of the CCSDS 123.0-B-1 Lossless Multispectral and Hyperspectral Image Compression Algorithm is presented. This recommended standard provides a tradeoff between compression performance and computational complexity, which makes it suitable for onboard applications. A High-Level Synthesis (HLS) methodology is followed to reduce the implementation time of this complex algorithm in hardware, providing a comparison between two of the main solutions available in the market: Mentor Catapult C and Xilinx Vivado HLS. The final implementation is tested over a Xilinx Zynq-7000 FPGA-based MPSoC. The obtained results show the good features of the HLS solutions compared with a RTL alternative of the standard, in terms of maximum clock frequency and resources utilization, hightlighting the quality of the current HLS tools to obtain the equivalent RTL description.