Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/63423
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Baez, Abelardo | en_US |
dc.contributor.author | Fabelo Gómez, Himar Antonio | en_US |
dc.contributor.author | Florimbi, Giordana | en_US |
dc.contributor.author | Torti, Emanuele | en_US |
dc.contributor.author | Hernandez, Abian | en_US |
dc.contributor.author | Leporati, Francesco | en_US |
dc.contributor.author | Danese, Giovanni | en_US |
dc.contributor.author | Sarmiento Rodríguez, Roberto | en_US |
dc.contributor.author | Ortega, Samuel | en_US |
dc.contributor.author | Callico, Gustavo M. | en_US |
dc.date.accessioned | 2020-01-22T10:26:34Z | - |
dc.date.available | 2020-01-22T10:26:34Z | - |
dc.date.issued | 2019 | en_US |
dc.identifier.issn | 2079-9292 | en_US |
dc.identifier.other | WoS | - |
dc.identifier.uri | http://hdl.handle.net/10553/63423 | - |
dc.description.abstract | Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations. | en_US |
dc.language | eng | en_US |
dc.relation | Identificación Hiperespectral de Tumores Cerebrales (Ithaca) | en_US |
dc.relation | Plataforma H2/Sw Distribuida Para El Procesamiento Inteligente de Información Sensorial Heterogenea en Aplicaciones de Supervisión de Grandes Espacios Naturales | en_US |
dc.relation.ispartof | Electronics (Switzerland) | en_US |
dc.source | Electronics [ISSN 2079-9292], v. 8(12), 1494 | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | High-Level Synthesis | en_US |
dc.subject.other | Hls | en_US |
dc.subject.other | Sdsoc | en_US |
dc.subject.other | Support Vector Machines | en_US |
dc.subject.other | Svm | en_US |
dc.subject.other | Code Refactoring | en_US |
dc.subject.other | Zynq | en_US |
dc.subject.other | Zedboard | en_US |
dc.title | High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images | en_US |
dc.type | info:eu-repo/semantics/article | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.3390/electronics8121494 | en_US |
dc.identifier.isi | 000506678200120 | - |
dc.identifier.issue | 12 | - |
dc.description.firstpage | 1494 | en_US |
dc.relation.volume | 8 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
local.message.claim | 2021-10-23T17:15:18.960+0100|||rp03104|||submit_approve|||dc_contributor_author|||None | * |
dc.contributor.daisngid | 12307505 | - |
dc.contributor.daisngid | 34770098 | - |
dc.contributor.daisngid | 31939674 | - |
dc.contributor.daisngid | 9760694 | - |
dc.contributor.daisngid | 34701780 | - |
dc.contributor.daisngid | 9114364 | - |
dc.contributor.daisngid | 797863 | - |
dc.contributor.daisngid | 30348763 | - |
dc.contributor.daisngid | 506422 | - |
dc.contributor.daisngid | 116294 | - |
dc.description.numberofpages | 17 | en_US |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:Baez, A | - |
dc.contributor.wosstandard | WOS:Fabelo, H | - |
dc.contributor.wosstandard | WOS:Ortega, S | - |
dc.contributor.wosstandard | WOS:Florimbi, G | - |
dc.contributor.wosstandard | WOS:Torti, E | - |
dc.contributor.wosstandard | WOS:Hernandez, A | - |
dc.contributor.wosstandard | WOS:Leporati, F | - |
dc.contributor.wosstandard | WOS:Danese, G | - |
dc.contributor.wosstandard | WOS:Callico, GM | - |
dc.contributor.wosstandard | WOS:Sarmiento, R | - |
dc.identifier.ulpgc | Sí | en_US |
dc.contributor.buulpgc | BU-TEL | en_US |
dc.description.sjr | 0,303 | |
dc.description.jcr | 2,412 | |
dc.description.sjrq | Q2 | |
dc.description.jcrq | Q2 | |
dc.description.scie | SCIE | |
item.fulltext | Con texto completo | - |
item.grantfulltext | open | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-9794-490X | - |
crisitem.author.orcid | 0000-0002-7519-954X | - |
crisitem.author.orcid | 0000-0002-2508-2845 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.orcid | 0000-0002-3784-5504 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Fabelo Gómez, Himar Antonio | - |
crisitem.author.fullName | Ortega Sarmiento,Samuel | - |
crisitem.author.fullName | Hernández Guedes, Abián | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
crisitem.author.fullName | Marrero Callicó, Gustavo Iván | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
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