|Title:||Noise margin enhancement in GaAs ROM's using current mode logic||Authors:||Lopez, JF
|Keywords:||Word||Issue Date:||1997||Publisher:||0018-9200||Journal:||IEEE Journal of Solid-State Circuits||Abstract:||Two different techniques that allow the implementation of embedded ROM's using a conventional GaAs MESFET technology are presented, The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM's because of its degradation as the number of word lines is increased, A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively, The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin.||URI:||http://hdl.handle.net/10553/53735||ISSN:||0018-9200||Source:||Ieee Journal Of Solid-State Circuits[ISSN 0018-9200],v. 32 (4), p. 592-597|
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