Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/53735
Campo DC Valoridioma
dc.contributor.authorLopez, JF
dc.contributor.authorSarmiento, R
dc.contributor.authorEshraghian, K
dc.contributor.authorNunez, A
dc.contributor.otherSarmiento, Roberto
dc.contributor.otherLopez, Jose
dc.date.accessioned2019-02-04T18:01:55Z-
dc.date.available2019-02-04T18:01:55Z-
dc.date.issued1997
dc.identifier.issn0018-9200
dc.identifier.urihttp://hdl.handle.net/10553/53735-
dc.description.abstractTwo different techniques that allow the implementation of embedded ROM's using a conventional GaAs MESFET technology are presented, The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM's because of its degradation as the number of word lines is increased, A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively, The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin.
dc.publisher0018-9200
dc.relation.ispartofIEEE Journal of Solid-State Circuits
dc.sourceIeee Journal Of Solid-State Circuits[ISSN 0018-9200],v. 32 (4), p. 592-597
dc.subject.otherWord
dc.titleNoise margin enhancement in GaAs ROM's using current mode logic
dc.typeinfo:eu-repo/semantics/Article
dc.typeArticle
dc.identifier.isiA1997WP15200015
dcterms.isPartOfIeee Journal Of Solid-State Circuits
dcterms.sourceIeee Journal Of Solid-State Circuits[ISSN 0018-9200],v. 32 (4), p. 592-597
dc.description.lastpage597
dc.identifier.issue4
dc.description.firstpage592
dc.relation.volume32
dc.type2Artículo
dc.identifier.wosWOS:A1997WP15200015
dc.contributor.daisngid846472
dc.contributor.daisngid116294
dc.contributor.daisngid228382
dc.contributor.daisngid33795
dc.identifier.investigatorRIDL-6017-2014
dc.identifier.investigatorRIDL-6046-2014
dc.contributor.wosstandardWOS:Lopez, JF
dc.contributor.wosstandardWOS:Sarmiento, R
dc.contributor.wosstandardWOS:Eshraghian, K
dc.contributor.wosstandardWOS:Nunez, A
dc.date.coverdateAbril 1997
dc.identifier.ulpgces
dc.description.jcr0,922
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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