Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/53613
Title: Timing Model For Sdcfl Digital Circuits
Authors: Gomez, L 
Hernandez, A
Nunez, A 
Keywords: Mos
Issue Date: 1992
Publisher: 0165-6074
Journal: Microprocessing and Microprogramming 
Abstract: In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an approximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9 %.
URI: http://hdl.handle.net/10553/53613
ISSN: 0165-6074
Source: Microprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196
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