Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/53613
| Título: | Timing Model For Sdcfl Digital Circuits | Autores/as: | Gomez, L Hernandez, A Nunez, A |
Palabras clave: | Mos | Fecha de publicación: | 1992 | Editor/a: | 0165-6074 | Publicación seriada: | Microprocessing and Microprogramming | Resumen: | In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an approximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9 %. | URI: | http://hdl.handle.net/10553/53613 | ISSN: | 0165-6074 | Fuente: | Microprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196 |
| Colección: | Artículos |
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