Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/53613
DC FieldValueLanguage
dc.contributor.authorGomez, L
dc.contributor.authorHernandez, A
dc.contributor.authorNunez, A
dc.contributor.otherGomez, Luis
dc.contributor.otherNunez, Antonio
dc.date.accessioned2019-02-04T17:25:51Z-
dc.date.available2019-02-04T17:25:51Z-
dc.date.issued1992
dc.identifier.issn0165-6074
dc.identifier.urihttp://hdl.handle.net/10553/53613-
dc.description.abstractIn this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an approximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9 %.
dc.publisher0165-6074
dc.relation.ispartofMicroprocessing and Microprogramming
dc.sourceMicroprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196
dc.subject.otherMos
dc.titleTiming Model For Sdcfl Digital Circuits
dc.typeinfo:eu-repo/semantics/Article
dc.typeArticle
dc.identifier.isiA1992HH65700045
dcterms.isPartOfMicroprocessing And Microprogramming
dcterms.sourceMicroprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196
dc.description.lastpage196
dc.identifier.issue1-5
dc.description.firstpage193
dc.relation.volume34
dc.type2Artículo
dc.identifier.wosWOS:A1992HH65700045
dc.contributor.daisngid746480
dc.contributor.daisngid32264118
dc.contributor.daisngid20654069
dc.contributor.daisngid33795
dc.identifier.investigatorRIDK-7777-2014
dc.identifier.investigatorRIDM-1726-2014
dc.contributor.wosstandardWOS:GOMEZ, L
dc.contributor.wosstandardWOS:HERNANDEZ, A
dc.contributor.wosstandardWOS:NUNEZ, A
dc.date.coverdateFebrero 1992
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUCES: Centro de Tecnologías de la Imagen-
crisitem.author.deptIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-0667-2302-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Ciencias y Tecnologías Cibernéticas-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGómez Déniz, Luis-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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