Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/53613
| Campo DC | Valor | idioma |
|---|---|---|
| dc.contributor.author | Gomez, L | |
| dc.contributor.author | Hernandez, A | |
| dc.contributor.author | Nunez, A | |
| dc.contributor.other | Gomez, Luis | |
| dc.contributor.other | Nunez, Antonio | |
| dc.date.accessioned | 2019-02-04T17:25:51Z | - |
| dc.date.available | 2019-02-04T17:25:51Z | - |
| dc.date.issued | 1992 | |
| dc.identifier.issn | 0165-6074 | |
| dc.identifier.uri | http://hdl.handle.net/10553/53613 | - |
| dc.description.abstract | In this work we present a timing analyzer suitable for dealing with GaAs MESFET SDCFL logic family and it uses inverters as an approximation for multiple input gates. The model consists in an adaptation from a developed methodology for NMOS and CMOS Si logic families. The model has been validated against SPICE simulations. Measured errors are lower than 9 %. | |
| dc.publisher | 0165-6074 | |
| dc.relation.ispartof | Microprocessing and Microprogramming | |
| dc.source | Microprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196 | |
| dc.subject.other | Mos | |
| dc.title | Timing Model For Sdcfl Digital Circuits | |
| dc.type | info:eu-repo/semantics/Article | |
| dc.type | Article | |
| dc.identifier.isi | A1992HH65700045 | |
| dcterms.isPartOf | Microprocessing And Microprogramming | |
| dcterms.source | Microprocessing And Microprogramming[ISSN 0165-6074],v. 34 (1-5), p. 193-196 | |
| dc.description.lastpage | 196 | |
| dc.identifier.issue | 1-5 | |
| dc.description.firstpage | 193 | |
| dc.relation.volume | 34 | |
| dc.type2 | Artículo | |
| dc.identifier.wos | WOS:A1992HH65700045 | |
| dc.contributor.daisngid | 746480 | |
| dc.contributor.daisngid | 32264118 | |
| dc.contributor.daisngid | 20654069 | |
| dc.contributor.daisngid | 33795 | |
| dc.identifier.investigatorRID | K-7777-2014 | |
| dc.identifier.investigatorRID | M-1726-2014 | |
| dc.contributor.wosstandard | WOS:GOMEZ, L | |
| dc.contributor.wosstandard | WOS:HERNANDEZ, A | |
| dc.contributor.wosstandard | WOS:NUNEZ, A | |
| dc.date.coverdate | Febrero 1992 | |
| dc.identifier.ulpgc | Sí | es |
| item.grantfulltext | none | - |
| item.fulltext | Sin texto completo | - |
| crisitem.author.dept | GIR IUCES: Centro de Tecnologías de la Imagen | - |
| crisitem.author.dept | IU de Cibernética, Empresa y Sociedad (IUCES) | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.orcid | 0000-0003-0667-2302 | - |
| crisitem.author.orcid | 0000-0003-1295-1594 | - |
| crisitem.author.parentorg | IU de Cibernética, Empresa y Sociedad (IUCES) | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.fullName | Gómez Déniz, Luis | - |
| crisitem.author.fullName | Núñez Ordóñez, Antonio | - |
| Colección: | Artículos | |
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