Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/52223
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dc.contributor.authorCelinski, Peteren_US
dc.contributor.authorLópez Feliciano, José Franciscoen_US
dc.contributor.authorAl-Sarawi, S.en_US
dc.contributor.authorAbbott, Dereken_US
dc.date.accessioned2018-11-25T18:28:48Z-
dc.date.available2018-11-25T18:28:48Z-
dc.date.issued2002en_US
dc.identifier.issn0026-2692en_US
dc.identifier.urihttp://hdl.handle.net/10553/52223-
dc.description.abstractThis paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth. carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate. (C) 2002 Published by Elsevier Science Ltd.
dc.languagespaen_US
dc.publisher0026-2692en_US
dc.relation.ispartofMicroelectronicsen_US
dc.sourceMicroelectronics Journal[ISSN 0026-2692],v. 33, p. 1071-1077en_US
dc.subject.otherGate
dc.titleLow depth, low power carry lookahead adders using threshold logicen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceConference on Electronics andStructures for MEMSen_US
dc.identifier.doi10.1016/S0026-2692(02)00112-Xen_US
dc.identifier.scopus0036896436-
dc.identifier.isi000179840200006-
dc.contributor.authorscopusid6701421283-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid7004170747-
dc.contributor.authorscopusid56053895400-
dc.description.lastpage1077en_US
dc.description.firstpage1071en_US
dc.relation.volume33en_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid2345841-
dc.contributor.daisngid2138004-
dc.contributor.daisngid256376-
dc.contributor.daisngid8183-
dc.contributor.wosstandardWOS:Celinski, P-
dc.contributor.wosstandardWOS:Lopez, JF-
dc.contributor.wosstandardWOS:Al-Sarawi, S-
dc.contributor.wosstandardWOS:Abbott, D-
dc.date.coverdateDiciembre 2002en_US
dc.identifier.conferenceidevents120317-
dc.identifier.ulpgces
dc.contributor.buulpgcBU-TELen_US
dc.description.jcr0,457
dc.description.jcrqQ3
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate17-12-2001-
crisitem.event.eventsenddate19-12-2001-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Feliciano, José Francisco-
Appears in Collections:Actas de congresos
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