Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/52223
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Celinski, Peter | en_US |
dc.contributor.author | López Feliciano, José Francisco | en_US |
dc.contributor.author | Al-Sarawi, S. | en_US |
dc.contributor.author | Abbott, Derek | en_US |
dc.date.accessioned | 2018-11-25T18:28:48Z | - |
dc.date.available | 2018-11-25T18:28:48Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.issn | 0026-2692 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/52223 | - |
dc.description.abstract | This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth. carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate. (C) 2002 Published by Elsevier Science Ltd. | |
dc.language | spa | en_US |
dc.publisher | 0026-2692 | en_US |
dc.relation.ispartof | Microelectronics | en_US |
dc.source | Microelectronics Journal[ISSN 0026-2692],v. 33, p. 1071-1077 | en_US |
dc.subject.other | Gate | |
dc.title | Low depth, low power carry lookahead adders using threshold logic | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | Conference on Electronics andStructures for MEMS | en_US |
dc.identifier.doi | 10.1016/S0026-2692(02)00112-X | en_US |
dc.identifier.scopus | 0036896436 | - |
dc.identifier.isi | 000179840200006 | - |
dc.contributor.authorscopusid | 6701421283 | - |
dc.contributor.authorscopusid | 7404444793 | - |
dc.contributor.authorscopusid | 7004170747 | - |
dc.contributor.authorscopusid | 56053895400 | - |
dc.description.lastpage | 1077 | en_US |
dc.description.firstpage | 1071 | en_US |
dc.relation.volume | 33 | en_US |
dc.type2 | Actas de congresos | en_US |
dc.contributor.daisngid | 2345841 | - |
dc.contributor.daisngid | 2138004 | - |
dc.contributor.daisngid | 256376 | - |
dc.contributor.daisngid | 8183 | - |
dc.contributor.wosstandard | WOS:Celinski, P | - |
dc.contributor.wosstandard | WOS:Lopez, JF | - |
dc.contributor.wosstandard | WOS:Al-Sarawi, S | - |
dc.contributor.wosstandard | WOS:Abbott, D | - |
dc.date.coverdate | Diciembre 2002 | en_US |
dc.identifier.conferenceid | events120317 | - |
dc.identifier.ulpgc | Sí | es |
dc.contributor.buulpgc | BU-TEL | en_US |
dc.description.jcr | 0,457 | |
dc.description.jcrq | Q3 | |
dc.description.scie | SCIE | |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.event.eventsstartdate | 17-12-2001 | - |
crisitem.event.eventsenddate | 19-12-2001 | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
Appears in Collections: | Actas de congresos |
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