Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/52223
Título: Low depth, low power carry lookahead adders using threshold logic
Autores/as: Celinski, Peter
López Feliciano, José Francisco 
Al-Sarawi, S.
Abbott, Derek
Palabras clave: Gate
Fecha de publicación: 2002
Editor/a: 0026-2692
Publicación seriada: Microelectronics 
Conferencia: Conference on Electronics andStructures for MEMS 
Resumen: This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth. carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate. (C) 2002 Published by Elsevier Science Ltd.
URI: http://hdl.handle.net/10553/52223
ISSN: 0026-2692
DOI: 10.1016/S0026-2692(02)00112-X
Fuente: Microelectronics Journal[ISSN 0026-2692],v. 33, p. 1071-1077
Colección:Actas de congresos
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