|Title:||State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications||Authors:||Celinski, Peter
Cotofana, Sorin D.
López, José F.
|Issue Date:||2003||Publisher:||0277-786X||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||VLSI Circuits and Systems||Abstract:||In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.||URI:||http://hdl.handle.net/10553/52222||ISSN:||0277-786X||DOI:||10.1117/12.497792||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 53-64|
|Appears in Collections:||Actas de congresos|
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