Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50492
Title: Runahead threads to improve SMT performance
Authors: Ramírez, Tanausú
Pajuelo, Alex
Santana, Oliverio J. 
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Issue Date: 2008
Publisher: 1530-0897
Journal: IEEE High-Performance Computer Architecture Symposium Proceedings 
Conference: 14th International Symposium on High-Performance Computer Architecture 
Abstract: In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation. ©2008 IEEE.
URI: http://hdl.handle.net/10553/50492
ISBN: 978-1-4244-2070-4
ISSN: 1530-0897
DOI: 10.1109/HPCA.2008.4658635
Source: 2008 Ieee 14Th International Symposium On High Peformance Computer Architecture [ISSN 1530-0897], p. 149-158, (2008)
Appears in Collections:Actas de congresos
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