Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/50492
Campo DC Valoridioma
dc.contributor.authorRamírez, Tanausúen_US
dc.contributor.authorPajuelo, Alexen_US
dc.contributor.authorSantana, Oliverio J.en_US
dc.contributor.authorValero, Mateoen_US
dc.date.accessioned2018-11-24T16:27:40Z-
dc.date.available2018-11-24T16:27:40Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2070-4en_US
dc.identifier.issn1530-0897en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/50492-
dc.description.abstractIn this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation. ©2008 IEEE.en_US
dc.languageengen_US
dc.publisher1530-0897en_US
dc.relation.ispartofIEEE High-Performance Computer Architecture Symposium Proceedingsen_US
dc.source2008 Ieee 14Th International Symposium On High Peformance Computer Architecture [ISSN 1530-0897], p. 149-158, (2008)en_US
dc.subject330406 Arquitectura de ordenadoresen_US
dc.titleRunahead threads to improve SMT performanceen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference14th International Symposium on High-Performance Computer Architectureen_US
dc.identifier.doi10.1109/HPCA.2008.4658635en_US
dc.identifier.scopus57749185053-
dc.identifier.isi000263593200013-
dc.contributor.authorscopusid35608297100-
dc.contributor.authorscopusid9733817100-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid24475914200-
dc.identifier.eissn2378-203X-
dc.description.lastpage158en_US
dc.identifier.issue4658635-
dc.description.firstpage149en_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid8417524-
dc.contributor.daisngid2739433-
dc.contributor.daisngid3401331-
dc.contributor.daisngid41870-
dc.description.numberofpages10en_US
dc.utils.revisionNoen_US
dc.contributor.wosstandardWOS:Ramirez, T-
dc.contributor.wosstandardWOS:Pajuelo, A-
dc.contributor.wosstandardWOS:Santana, OJ-
dc.contributor.wosstandardWOS:Valero, M-
dc.date.coverdateDiciembre 2008en_US
dc.identifier.conferenceidevents120655-
dc.identifier.ulpgces
dc.description.ggs1
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptGIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
crisitem.event.eventsstartdate16-02-2008-
crisitem.event.eventsenddate20-02-2008-
Colección:Actas de congresos
miniatura
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