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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49676
DC FieldValueLanguage
dc.contributor.authorNavarro-Botello, Victoren_US
dc.contributor.authorMontiel-Nelson, Juan A.en_US
dc.contributor.authorNooshabadi, Saeiden_US
dc.contributor.authorDyer, Mikeen_US
dc.date.accessioned2018-11-24T09:49:02Z-
dc.date.available2018-11-24T09:49:02Z-
dc.date.issued2006en_US
dc.identifier.isbn1424401739en_US
dc.identifier.issn1548-3746en_US
dc.identifier.urihttp://hdl.handle.net/10553/49676-
dc.description.abstractThis paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) [1] concept. Low power FTL arithmetic circuits provide for smaller propagation time delay (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies.en_US
dc.languageengen_US
dc.relation.ispartofMidwest Symposium on Circuits and Systemsen_US
dc.sourceMidwest Symposium on Circuits and Systems[ISSN 1548-3746],v. 1 (4267238), p. 709-712en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherCMOS logic circuitsen_US
dc.subject.otherCMOS technologyen_US
dc.subject.otherLogic designen_US
dc.subject.otherEnergy consumptionen_US
dc.subject.otherDelay effectsen_US
dc.subject.otherAddersen_US
dc.subject.otherPulse invertersen_US
dc.titleLow power arithmetic circuits in feedthrough dynamic CMOS logicen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference49th IEEE International Midwest Symposium on Circuits and Systemsen_US
dc.identifier.doi10.1109/MWSCAS.2006.382161en_US
dc.identifier.scopus34748814838-
dc.identifier.isi000248117800147-
dc.contributor.authorscopusid16402360500-
dc.contributor.authorscopusid6603626866-
dc.contributor.authorscopusid6602486254-
dc.contributor.authorscopusid57196887770-
dc.description.lastpage712en_US
dc.identifier.issue4267238-
dc.description.firstpage709en_US
dc.relation.volume1en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid5213989-
dc.contributor.daisngid480589-
dc.contributor.daisngid184255-
dc.contributor.daisngid9377717-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Navarro-Botello, V-
dc.contributor.wosstandardWOS:Montiel-Nelson, JA-
dc.contributor.wosstandardWOS:Nooshabadi, S-
dc.contributor.wosstandardWOS:Dyer, M-
dc.date.coverdateDiciembre 2006en_US
dc.identifier.conferenceidevents120564-
dc.identifier.conferenceidevents121327-
dc.identifier.ulpgcSíes
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate06-08-2006-
crisitem.event.eventsenddate09-08-2007-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-4323-8097-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameNavarro Botello, Victor-
crisitem.author.fullNameMontiel Nelson, Juan Antonio-
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