Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/49658
Título: On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects
Autores/as: García, José C. 
Montiel-Nelson, Juan A. 
Nooshabadi, Saeid
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Bus drivers
Low power signaling
Low power interconnect
Level converter
Fecha de publicación: 2009
Publicación seriada: Analog Integrated Circuits and Signal Processing 
Conferencia: 50th Midwest Symposium on Circuits and Systems 
Resumen: This paper reports a series of symmetric high performance, low to full swing level converters (udld1-converter to udld5-converter) for recovering signal levels at the receiver end of the global interconnects with large capacitive loads. The proposed udld5-converter provides a matching receiver for the up-down low swing voltage driver (UDLD) signaling style for driving the global interconnect lines. When implemented on 0.13 mu m CMOS 1.2 V technology, the udld5-converter performs 16% faster, reduces the energy per switching event by 4%, the energy-delay product by 19%, and the active area by 10%, when compared with a counterpart up low swing voltage driver (ULD) level converter (uld-converter). The proposed level converter receivers, each provide a different performance energy saving trade off. The paper also provides comparative performance evaluation of the various proposed level converters and uld-converter.
URI: http://hdl.handle.net/10553/49658
ISSN: 0925-1030
DOI: 10.1007/s10470-008-9209-2
Fuente: Analog Integrated Circuits and Signal Processing[ISSN 0925-1030],v. 60, p. 35-42
Colección:Actas de congresos
Vista completa

Visitas

17
actualizado el 04-feb-2023

Google ScholarTM

Verifica

Altmetric


Comparte



Exporta metadatos



Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.