On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects

Abstract

This paper reports a series of symmetric high performance, low to full swing level converters (udld1-converter to udld5-converter) for recovering signal levels at the receiver end of the global interconnects with large capacitive loads. The proposed udld5-converter provides a matching receiver for the up-down low swing voltage driver (UDLD) signaling style for driving the global interconnect lines. When implemented on 0.13 mu m CMOS 1.2 V technology, the udld5-converter performs 16% faster, reduces the energy per switching event by 4%, the energy-delay product by 19%, and the active area by 10%, when compared with a counterpart up low swing voltage driver (ULD) level converter (uld-converter). The proposed level converter receivers, each provide a different performance energy saving trade off. The paper also provides comparative performance evaluation of the various proposed level converters and uld-converter.