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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49654
DC FieldValueLanguage
dc.contributor.authorGarcía, José C.en_US
dc.contributor.authorMontiel-Nelson, Juan A.en_US
dc.contributor.authorNooshabadi, Saeiden_US
dc.contributor.otherMontiel-Nelson, Juan-
dc.date.accessioned2018-11-24T09:39:11Z-
dc.date.available2018-11-24T09:39:11Z-
dc.date.issued2009en_US
dc.identifier.isbn9780769537825en_US
dc.identifier.urihttp://hdl.handle.net/10553/49654-
dc.description.abstractThis paper presents the design of a highly efficient CMOS 2-input NAND (gcr-nand). When implemented on a 65nm CMOS technology, under 1pF capacitive loading condition, gcr-nand has a lower active area (3.4 times lower), and energy-delay product (56%) than the reference 2-input NAND (Iscpl-nand). Furthermore, gcr-nand is able to operate under a high output load.en_US
dc.languageengen_US
dc.relation.ispartof12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009en_US
dc.source12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 (5350167), p. 593-596en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherLow-voltageen_US
dc.subject.otherlow-energyen_US
dc.subject.otherhigh capacitive loaden_US
dc.subject.othercharge-recyclingen_US
dc.titleHigh performance CMOS 2-input NAND based on low-race split-level charge-recycling pass-transistor logicen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference12th Euromicro Conference on Digital System Design, Architectures, Methods and Toolsen_US
dc.identifier.doi10.1109/DSD.2009.181en_US
dc.identifier.scopus74549172975-
dc.identifier.isi000275715100077-
dcterms.isPartOfProceedings Of The 2009 12Th Euromicro Conference On Digital System Design, Architectures, Methods And Tools-
dcterms.sourceProceedings Of The 2009 12Th Euromicro Conference On Digital System Design, Architectures, Methods And Tools, p. 593-+-
dc.contributor.authorscopusid9639270900-
dc.contributor.authorscopusid6603626866-
dc.contributor.authorscopusid6602486254-
dc.description.lastpage596en_US
dc.identifier.issue5350167-
dc.description.firstpage593en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:000275715100077-
dc.contributor.daisngid29357666-
dc.contributor.daisngid1897928-
dc.contributor.daisngid480589-
dc.contributor.daisngid184255-
dc.identifier.investigatorRIDK-6805-2013-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Garcia, JC-
dc.contributor.wosstandardWOS:Montiel-Nelson, JA-
dc.contributor.wosstandardWOS:Nooshabadi, S-
dc.date.coverdateDiciembre 2009en_US
dc.identifier.conferenceidevents120706-
dc.identifier.ulpgcSíes
item.fulltextCon texto completo-
item.grantfulltextopen-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-4323-8097-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGarcía Montesdeoca,José Carlos-
crisitem.author.fullNameMontiel Nelson, Juan Antonio-
crisitem.event.eventsstartdate27-08-2009-
crisitem.event.eventsenddate29-08-2009-
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