Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49297
Title: Quantitative study of the impact of design and synthesis options on processor core performance
Authors: Bautista, T. 
Núñez, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: System-on-a-chip
Very large scale integration
Microarchitecture
Clocks
Design optimization, et al
Issue Date: 2001
Publisher: 1063-8210
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems 
Abstract: In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-mum, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL, descriptions.
URI: http://hdl.handle.net/10553/49297
ISSN: 1063-8210
DOI: 10.1109/92.929580
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems[ISSN 1063-8210],v. 9, p. 461-473
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