Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/49297
Campo DC Valoridioma
dc.contributor.authorBautista, T.en_US
dc.contributor.authorNúñez, A.en_US
dc.contributor.otherBautista, Tomas-
dc.date.accessioned2018-11-24T06:01:27Z-
dc.date.available2018-11-24T06:01:27Z-
dc.date.issued2001en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://hdl.handle.net/10553/49297-
dc.description.abstractIn this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-mum, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL, descriptions.en_US
dc.languageengen_US
dc.publisher1063-8210-
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.sourceIEEE Transactions on Very Large Scale Integration (VLSI) Systems[ISSN 1063-8210],v. 9, p. 461-473en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherSystem-on-a-chipen_US
dc.subject.otherVery large scale integrationen_US
dc.subject.otherMicroarchitectureen_US
dc.subject.otherClocksen_US
dc.subject.otherDesign optimizationen_US
dc.subject.otherDesign methodoogyen_US
dc.subject.otherIntellectual propertyen_US
dc.titleQuantitative study of the impact of design and synthesis options on processor core performanceen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/92.929580en_US
dc.identifier.scopus0035361796-
dc.identifier.isi000169453100005-
dcterms.isPartOfIeee Transactions On Very Large Scale Integration (Vlsi) Systems-
dcterms.sourceIeee Transactions On Very Large Scale Integration (Vlsi) Systems[ISSN 1063-8210],v. 9 (3), p. 461-473-
dc.contributor.authorscopusid6603190709-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage473en_US
dc.description.firstpage461en_US
dc.relation.volume9en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:000169453100005-
dc.contributor.daisngid2227678-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDA-9082-2011-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Bautista, T-
dc.contributor.wosstandardWOS:Nunez, A-
dc.date.coverdateJunio 2001en_US
dc.identifier.ulpgces
dc.description.jcr0,849
dc.description.jcrqQ2
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-5368-3680-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameBautista Delgado, Tomás-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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