Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/49297
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Bautista, T. | en_US |
dc.contributor.author | Núñez, A. | en_US |
dc.contributor.other | Bautista, Tomas | - |
dc.date.accessioned | 2018-11-24T06:01:27Z | - |
dc.date.available | 2018-11-24T06:01:27Z | - |
dc.date.issued | 2001 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/49297 | - |
dc.description.abstract | In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-mum, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL, descriptions. | en_US |
dc.language | eng | en_US |
dc.publisher | 1063-8210 | - |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | en_US |
dc.source | IEEE Transactions on Very Large Scale Integration (VLSI) Systems[ISSN 1063-8210],v. 9, p. 461-473 | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | System-on-a-chip | en_US |
dc.subject.other | Very large scale integration | en_US |
dc.subject.other | Microarchitecture | en_US |
dc.subject.other | Clocks | en_US |
dc.subject.other | Design optimization | en_US |
dc.subject.other | Design methodoogy | en_US |
dc.subject.other | Intellectual property | en_US |
dc.title | Quantitative study of the impact of design and synthesis options on processor core performance | en_US |
dc.type | info:eu-repo/semantics/Article | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/92.929580 | en_US |
dc.identifier.scopus | 0035361796 | - |
dc.identifier.isi | 000169453100005 | - |
dcterms.isPartOf | Ieee Transactions On Very Large Scale Integration (Vlsi) Systems | - |
dcterms.source | Ieee Transactions On Very Large Scale Integration (Vlsi) Systems[ISSN 1063-8210],v. 9 (3), p. 461-473 | - |
dc.contributor.authorscopusid | 6603190709 | - |
dc.contributor.authorscopusid | 7103279517 | - |
dc.description.lastpage | 473 | en_US |
dc.description.firstpage | 461 | en_US |
dc.relation.volume | 9 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Artículo | en_US |
dc.identifier.wos | WOS:000169453100005 | - |
dc.contributor.daisngid | 2227678 | - |
dc.contributor.daisngid | 33795 | - |
dc.identifier.investigatorRID | A-9082-2011 | - |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:Bautista, T | - |
dc.contributor.wosstandard | WOS:Nunez, A | - |
dc.date.coverdate | Junio 2001 | en_US |
dc.identifier.ulpgc | Sí | es |
dc.description.jcr | 0,849 | |
dc.description.jcrq | Q2 | |
dc.description.scie | SCIE | |
item.fulltext | Sin texto completo | - |
item.grantfulltext | none | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-5368-3680 | - |
crisitem.author.orcid | 0000-0003-1295-1594 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Bautista Delgado, Tomás | - |
crisitem.author.fullName | Núñez Ordóñez, Antonio | - |
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