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Please use this identifier to cite or link to this item: https://accedacris.ulpgc.es/handle/10553/49290
DC FieldValueLanguage
dc.contributor.authorJia, Z. J.en_US
dc.contributor.authorBautista, T.en_US
dc.contributor.authorNúñez, A.en_US
dc.contributor.otherBautista, Tomas-
dc.date.accessioned2018-11-24T05:57:04Z-
dc.date.available2018-11-24T05:57:04Z-
dc.date.issued2009en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttps://accedacris.ulpgc.es/handle/10553/49290-
dc.description.abstractA new static mapping technique is presented that can be integrated in a system-level design tool for modelling and simulating real-time applications onto an embedded multiprocessor system. The results of preliminary experiments indicate that the proposed two-phase mapping approach can achieve a good trade-off between the efficiency in resource usage and processor load balancing, as well as the minimisation of the inter-processor communication cost.en_US
dc.languageengen_US
dc.publisher0013-5194-
dc.relation.ispartofElectronics lettersen_US
dc.sourceElectronics Letters[ISSN 0013-5194],v. 45, p. 613-615en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherembedded systemsen_US
dc.subject.otherlogic designen_US
dc.subject.othermicroprocessor chipsen_US
dc.subject.otherSystem-on-chipen_US
dc.subject.otherresource allocationen_US
dc.titleReal-time application to multiprocessor-system-on-chip mapping strategy for system-level design toolen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el.2009.0952en_US
dc.identifier.scopus67149116623-
dc.identifier.isi000267820500022-
dcterms.isPartOfElectronics Letters-
dcterms.sourceElectronics Letters[ISSN 0013-5194],v. 45 (12), p. 613-614-
dc.contributor.authorscopusid55434973300-
dc.contributor.authorscopusid6603190709-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage615en_US
dc.description.firstpage613en_US
dc.relation.volume45en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:000267820500022-
dc.contributor.daisngid10393233-
dc.contributor.daisngid2227678-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDA-9082-2011-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Jia, ZJ-
dc.contributor.wosstandardWOS:Bautista, T-
dc.contributor.wosstandardWOS:Nunez, A-
dc.date.coverdateJunio 2009en_US
dc.identifier.ulpgcSíes
dc.description.sjr0,665
dc.description.jcr0,97
dc.description.sjrqQ1
dc.description.jcrqQ3
dc.description.scieSCIE
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-5368-3680-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameBautista Delgado, Tomás-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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