Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/48908
Title: A method of generating trust-worthy performance estimations for soft-IPs
Authors: Marrero Martín, Margarita 
Carballo, Pedro P. 
Núñez, Antonio 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Logic
Clocks
Transistors
System-on-chip
Computer aided design
Instrument modeling
Interference (communication)
Issue Date: 2003
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: Conference on VLSI Circuits and Systems 
Abstract: At 0.25, 0.18 mum processes and beyond important process variations occur not only from one fab to another among batches. Moreover as we approach the realm of deep-submicron design, process variations even across a single die are predicted to become a major source of spread. Reduced signal levels, noise margins and timing windows are all contributing to make previously minor variations in geometry and technological parameters a big issue for circuit design. Worse still, new mechanisms appear that cause important variations not only in transistors but also in interconnect. And some of those mechanisms, show greater variation across a single die than across similar structures on different dice from a wafer. Thus the chip designer must expect significant and not necessarily predictable differences between transistors and between interconnect resistances on a single die. Given this scenario widely recognised by process engineers, and given the additional spread built-in in the process of mapping from a soft IP design to a hard IP block, if the designer had the opportunity to know certain performance parameters of the final hardcores without doing successive synthesis it would lead to an easier and more predictable and accurate integration of the blocks in the system. In this sense, pre-characterised trust-worthy soft-IP blocks would be preferred candidates to select. We have explored ways for quantifying and analysing the synthesis to layout spread so that, instead of modelling the spread in devices and interconnects, we model and quantify at a higher abstraction level the technology mapping process as a whole, for a set of seed designs that will give bounds and guidelines for the behaviour of other designs when they are mapped to the same technology. For that purpose, only the best-, typical-, worst-case and other process variation corners need to be known. The analysis is based in the actual measured spread of reference seed designs as they experience spread when passing from soft to hard designs.
URI: http://hdl.handle.net/10553/48908
ISBN: 0-8194-4977-6
ISSN: 0277-786X
DOI: 10.1117/12.499074
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 610-617
Appears in Collections:Actas de congresos
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