Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/48908
DC FieldValueLanguage
dc.contributor.authorMarrero Martín, Margaritaen_US
dc.contributor.authorCarballo, Pedro P.en_US
dc.contributor.authorNúñez, Antonioen_US
dc.contributor.otherP. Carballo, Pedro-
dc.date.accessioned2018-11-24T02:02:50Z-
dc.date.available2018-11-24T02:02:50Z-
dc.date.issued2003en_US
dc.identifier.isbn0-8194-4977-6en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/10553/48908-
dc.description.abstractAt 0.25, 0.18 mum processes and beyond important process variations occur not only from one fab to another among batches. Moreover as we approach the realm of deep-submicron design, process variations even across a single die are predicted to become a major source of spread. Reduced signal levels, noise margins and timing windows are all contributing to make previously minor variations in geometry and technological parameters a big issue for circuit design. Worse still, new mechanisms appear that cause important variations not only in transistors but also in interconnect. And some of those mechanisms, show greater variation across a single die than across similar structures on different dice from a wafer. Thus the chip designer must expect significant and not necessarily predictable differences between transistors and between interconnect resistances on a single die. Given this scenario widely recognised by process engineers, and given the additional spread built-in in the process of mapping from a soft IP design to a hard IP block, if the designer had the opportunity to know certain performance parameters of the final hardcores without doing successive synthesis it would lead to an easier and more predictable and accurate integration of the blocks in the system. In this sense, pre-characterised trust-worthy soft-IP blocks would be preferred candidates to select. We have explored ways for quantifying and analysing the synthesis to layout spread so that, instead of modelling the spread in devices and interconnects, we model and quantify at a higher abstraction level the technology mapping process as a whole, for a set of seed designs that will give bounds and guidelines for the behaviour of other designs when they are mapped to the same technology. For that purpose, only the best-, typical-, worst-case and other process variation corners need to be known. The analysis is based in the actual measured spread of reference seed designs as they experience spread when passing from soft to hard designs.en_US
dc.languageengen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.sourceProceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 610-617en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherLogicen_US
dc.subject.otherClocksen_US
dc.subject.otherTransistorsen_US
dc.subject.otherSystem-on-chipen_US
dc.subject.otherComputer aided designen_US
dc.subject.otherInstrument modelingen_US
dc.subject.otherInterference (communication)en_US
dc.titleA method of generating trust-worthy performance estimations for soft-IPsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceConference on VLSI Circuits and Systemsen_US
dc.identifier.doi10.1117/12.499074en_US
dc.identifier.scopus0042829443-
dc.identifier.isi000183950600062-
dcterms.isPartOfVlsi Circuits And Systems-
dcterms.sourceVlsi Circuits And Systems[ISSN 0277-786X],v. 5117, p. 610-617-
dc.contributor.authorscopusid7005760245-
dc.contributor.authorscopusid6602499289-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage617en_US
dc.description.firstpage610en_US
dc.relation.volume5117en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:000183950600062-
dc.contributor.daisngid13620817-
dc.contributor.daisngid2969956-
dc.contributor.daisngid3056889-
dc.contributor.daisngid10359097-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDF-6600-2014-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Marrero, M-
dc.contributor.wosstandardWOS:Carballo, PP-
dc.contributor.wosstandardWOS:Nunez, A-
dc.date.coverdateSeptiembre 2003en_US
dc.identifier.conferenceidevents120355-
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-0861-9954-
crisitem.author.orcid0000-0001-7912-8768-
crisitem.author.orcid0000-0001-7912-8768-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameMarrero Martín, Margarita Luisa-
crisitem.author.fullNamePérez Carballo, Pedro Francisco-
crisitem.author.fullNamePérez Carballo, Pedro Francisco-
crisitem.event.eventsstartdate19-05-2003-
crisitem.event.eventsenddate21-05-2003-
Appears in Collections:Actas de congresos
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