|Title:||Accelerating a MPEG-4 video decoder through custom software/hardware co-design||Authors:||Díaz, Jorge L.
Carballo, Pedro P.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Field programmable gate arrays
Super resolution, et al
|Issue Date:||2007||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||Conference on VLSI Circuits and Systems III||Abstract:||In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel mu C/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.||URI:||http://hdl.handle.net/10553/48904||ISBN:||978-0-8194-6718-8||ISSN:||0277-786X||DOI:||10.1117/12.722068||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 6590 (65900B)|
|Appears in Collections:||Actas de congresos|
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