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http://hdl.handle.net/10553/48902
Title: | ESL flow for a hardware H.264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study | Authors: | Thadani, M. Carballo, P. P. Hernández-Fernández, Pedro Marrero, G. Núñez, A. |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | Electronic System Level high-level synthesis SystemC TLM-2.0 logic synthesis FPGA |
Issue Date: | 2009 | Journal: | Proceedings of SPIE - The International Society for Optical Engineering | Conference: | Conference on VLSI Circuits and Systems IV | Abstract: | The present paper describes an Electronic System Level (ESL) design methodology which was established and employed in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time requirements for QCIF frames. | URI: | http://hdl.handle.net/10553/48902 | ISBN: | 9780819476371 | ISSN: | 0277-786X | DOI: | 10.1117/12.821647 | Source: | Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 7363 (73630K) |
Appears in Collections: | Actas de congresos |
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