Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/47684
Title: High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems
Authors: Dias, Tiago
Lopez, Sebastian 
Roma, Nuno
Sousa, Leonel
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Video coding
Image sequences
Arrays
Kernel
Embedded systems
Issue Date: 2011
Journal: Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011
Abstract: An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV.
URI: http://hdl.handle.net/10553/47684
ISBN: 9781457708008
DOI: 10.1109/SAMOS.2011.6045465
Source: Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011 (6045465), p. 225-232
Appears in Collections:Actas de congresos
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