Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/47684
Campo DC Valoridioma
dc.contributor.authorDias, Tiagoen_US
dc.contributor.authorLopez, Sebastianen_US
dc.contributor.authorRoma, Nunoen_US
dc.contributor.authorSousa, Leonelen_US
dc.date.accessioned2018-11-23T15:33:54Z-
dc.date.available2018-11-23T15:33:54Z-
dc.date.issued2011en_US
dc.identifier.isbn9781457708008en_US
dc.identifier.urihttp://hdl.handle.net/10553/47684-
dc.description.abstractAn innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011en_US
dc.sourceProceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011 (6045465), p. 225-232en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherVideo codingen_US
dc.subject.otherImage sequencesen_US
dc.subject.otherArraysen_US
dc.subject.otherKernelen_US
dc.subject.otherEmbedded systemsen_US
dc.titleHigh throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systemsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.identifier.doi10.1109/SAMOS.2011.6045465en_US
dc.identifier.scopus80155210115-
dc.contributor.authorscopusid35093983900-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid6602399540-
dc.contributor.authorscopusid7004775548-
dc.description.lastpage232en_US
dc.identifier.issue6045465-
dc.description.firstpage225en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.utils.revisionen_US
dc.identifier.ulpgces
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
Colección:Actas de congresos
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