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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/47620
DC FieldValueLanguage
dc.contributor.authorGómez, L.en_US
dc.contributor.authorHernández Ballester, Antonioen_US
dc.contributor.authorNunez, A.en_US
dc.contributor.otherGomez, Luis-
dc.date.accessioned2018-11-23T15:01:20Z-
dc.date.available2018-11-23T15:01:20Z-
dc.date.issued1993en_US
dc.identifier.issn0165-6074en_US
dc.identifier.urihttp://hdl.handle.net/10553/47620-
dc.description.abstractA methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15 % error and with a speed-up of four orders of magnitude for several circuits tested as compared with HSPICE simulations.en_US
dc.languageengen_US
dc.publisher0165-6074-
dc.relation.ispartofMicroprocessing and Microprogrammingen_US
dc.sourceMicroprocessing and Microprogramming[ISSN 0165-6074],v. 38, p. 511-518en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.othertiming analyzeren_US
dc.subject.otherDCFL/SDCFL GaAsen_US
dc.subject.otherDelayen_US
dc.titleTiming analysis for DCFL/SDCFL VLSI circuitsen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.relation.conference19TH EUROMICRO SYMP ON MICROPROCESSING AND MICROPROGRAMMING ( EUROMICRO 93 )-
dc.identifier.doi10.1016/0165-6074(93)90189-Ren_US
dc.identifier.scopus0027657309-
dc.identifier.isiA1993LT48300076-
dcterms.isPartOfMicroprocessing And Microprogramming-
dcterms.sourceMicroprocessing And Microprogramming[ISSN 0165-6074],v. 38 (1-5), p. 511-518-
dc.contributor.authorscopusid56789548300-
dc.contributor.authorscopusid57194681887-
dc.contributor.authorscopusid7103279517-
dc.description.lastpage518en_US
dc.description.firstpage511en_US
dc.relation.volume38en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:A1993LT48300076-
dc.contributor.daisngid746480-
dc.contributor.daisngid32264118-
dc.contributor.daisngid14111628-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDK-7777-2014-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:GOMEZ, L-
dc.contributor.wosstandardWOS:HERNANDEZ, A-
dc.contributor.wosstandardWOS:NUNEZ, A-
dc.date.coverdateEnero 1993en_US
dc.identifier.conferenceidevents121199-
dc.identifier.ulpgcSíes
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate06-09-1993-
crisitem.event.eventsenddate09-09-1993-
crisitem.author.deptGIR IUCES: Centro de Tecnologías de la Imagen-
crisitem.author.deptIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-0667-2302-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Cibernética, Empresa y Sociedad (IUCES)-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGómez Déniz, Luis-
crisitem.author.fullNameHernández Ballester, Antonio-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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