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http://hdl.handle.net/10553/47620
| Título: | Timing analysis for DCFL/SDCFL VLSI circuits | Autores/as: | Gómez, L. Hernández Ballester, Antonio Nunez, A. |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | timing analyzer DCFL/SDCFL GaAs Delay |
Fecha de publicación: | 1993 | Editor/a: | 0165-6074 | Publicación seriada: | Microprocessing and Microprogramming | Conferencia: | 19TH EUROMICRO SYMP ON MICROPROCESSING AND MICROPROGRAMMING ( EUROMICRO 93 ) | Resumen: | A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15 % error and with a speed-up of four orders of magnitude for several circuits tested as compared with HSPICE simulations. | URI: | http://hdl.handle.net/10553/47620 | ISSN: | 0165-6074 | DOI: | 10.1016/0165-6074(93)90189-R | Fuente: | Microprocessing and Microprogramming[ISSN 0165-6074],v. 38, p. 511-518 |
| Colección: | Artículos |
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