Please use this identifier to cite or link to this item:
https://accedacris.ulpgc.es/handle/10553/47620
| Title: | Timing analysis for DCFL/SDCFL VLSI circuits |
| Authors: | Gómez, L. Hernández Ballester, Antonio Nunez, A. |
| UNESCO Clasification: | 3307 Tecnología electrónica |
| Keywords: | timing analyzer DCFL/SDCFL GaAs Delay |
| Issue Date: | 1993 |
| Publisher: | 0165-6074 |
| Journal: | Microprocessing and Microprogramming |
| Conference: | 19TH EUROMICRO SYMP ON MICROPROCESSING AND MICROPROGRAMMING ( EUROMICRO 93 ) |
| Abstract: | A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15 % error and with a speed-up of four orders of magnitude for several circuits tested as compared with HSPICE simulations. |
| URI: | https://accedacris.ulpgc.es/handle/10553/47620 |
| ISSN: | 0165-6074 |
| DOI: | 10.1016/0165-6074(93)90189-R |
| Source: | Microprocessing and Microprogramming[ISSN 0165-6074],v. 38, p. 511-518 |
| Appears in Collections: | Articles |
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