Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/47599
Title: Area reduction techniques for full integrated distributed amplifier
Authors: Del Pino, J. 
Diaz, R.
Khemchandani, S. L. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Spiral Inductors
Cmos
Technology
Design
Issue Date: 2010
Publisher: 1434-8411
Journal: AEU - International Journal of Electronics and Communications 
Abstract: This paper presents two techniques to reduce the area in the design of CMOS distributed amplifiers. The proposed techniques take into account the influence of compacting the layout and the use of stacked inductor for the artificial transmission lines on the distributed amplifier performance. Following these design guidelines, three prototypes have been fabricated in a low cost CMOS 0 35 mu m process. The measured gain is about 6 dB with a cutoff frequency around 8 GHz. The noise figure varies from 5 to 7 dB and the circuits draw 30 mA from a 3.3 V voltage supply. With the developed area optimization design techniques, a maximum area reduction of 37% with respect to a conventional design has been achieved, without any significant performance degradation. (C) 2010 Elsevier GmbH All rights reserved.
URI: http://hdl.handle.net/10553/47599
ISSN: 1434-8411
DOI: 10.1016/j.aeue.2009.12.006
Source: AEU - International Journal of Electronics and Communications[ISSN 1434-8411],v. 64, p. 1055-1062
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